Programmable logic devices (PLDs) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. In CPLDs, configuration data is typically stored on-chip in non-volatile memory. In some CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration (programming) sequence.
For all of these PLDs, the functionality of the device is controlled by data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, e.g., using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as devices that are only partially programmable. For example, one type of PLD includes a combination of hard-coded transistor logic and a programmable switch fabric that programmably interconnects the hard-coded transistor logic.
PLDs have become commonplace within a variety of different types of systems. Often, the PLD is incorporated into a system that includes a primary processor, e.g., a microprocessor, as well as one or more peripheral devices. The PLD, for example, may be disposed within the system as an interface linking the peripheral devices with the primary processor. When not in use, the PLD may be powered down or placed in a low power mode. When in a low power mode, signals passed into the PLD, e.g., from a peripheral device, the processor, or another source, are not passed back out to other devices. This means that when placed in low power mode, the PLD no longer functions as an interface. The PLD effectively becomes an open circuit in that signals are not passed in, out, or through the device
In illustration, consider the case where signals from a peripheral device are coupled to the PLD. The PLD functions as an interface between the peripheral device and another processor. Signals from the peripheral device that are coupled to the PLD may also be used to “wake-up” the processor from a low power mode. When the processor is in a low power mode, power consumption can be further reduced if the PLD is also placed in a low power mode. When placed in a low power mode, however, the PLD cannot pass the signals needed to “wake-up” the processor. Accordingly, alternate channels external to the PLD must be provided to allow such signals to propagate to the processor when the PLD is in a low power mode.
In other examples, it may be desirable to place the PLD in a low power mode and, under certain circumstances, provide a signal to another device, e.g., a processor. While the PLD is placed in a low power mode, the processor may or may not be operating in a low power mode. In any case, the signals to be provided to the processor would not be passed through the PLD. Further, as noted, an alternate channel that is external to the PLD would have to be provided to couple the peripheral device with the processor when the PLD is in low power mode.